This invention relates to control circuits for matrix drive recording in a dot printer and particularly to a control circuit suitable for various desirable dot-print patterns under a print scheme of matrix-driven printing heads.
A conventional control circuit for matrix drive recording often employs a minimum number of drive circuits for the matrix, that is 2.sqroot.N drive circuits for a square matrix having the square root of N as one side where N is the number of recording heads.
There has been proposed a use of a modified matrix combination for speeding-up of the total system utilizing a low-speed recording unit such as heat-sensitive recording means, for example, use of (l, m, n) combination type drive circuits for a matrix of (l, m, n) arrangement.
However, in order to prevent the conspicuous discontinuity of recording in this matrix arrangement, there is used a method of further modifying the combination.
A conventional method of modifying the matrix combination will be described with reference to FIGS. 1 to 3.
FIG. 1 is a circuit diagram of recording heads connected in a modified matrix arrangement, and FIG. 2 shows an example in which the discontinuity of recording is improved by use of the circuit arrangement of FIG. 1, and FIG. 3 shows an example of a conventional recording control circuit.
In FIG. 1, the circuit arrangement has 5.times.3.times.2, namely 30 heat-generating elements for the (l, m, n) matrix where l=5, m=3 and n=2. Referring to FIG. 1, there are shown heat generating elements 11 (11.sub.1 to 11.sub.3) picture image input terminals 13 (13.sub.1 to 13.sub.6), and common electrodes 12 (12.sub.1 to 12.sub.10) of 3 heat generating elements. If a recorded picture as shown in FIG. 2 is produced by the recording heads in FIG. 1, the discontinuity of recording in the scanning line becomes inconspicuous. In other words, if the left 5 blocks in FIG. 1 start to record in turn from the leftmost block and at the same time the right 5 blocks similarly start to record in turn from the rightmost block, the line as shown in FIG. 2 is recorded.
FIG. 3 shows an embodiment of a recording control circuit for causing such a recording operation.
Referring to FIG. 3, numeral 22 represents a recording head with common electrodes 27 to which the output from an oscillator 23 is applied through decoders 25a and 25b and drivers 26a and 26b, and with picture signal terminals 21 to which each of two halves of a signal corresponding to one scanning line, from a picture signal generator 15 is applied through RAMs (random access memories) 18a and 18b and shift registers 19a and 19b. RAMs 18c and 18d are supplied with the halves of the next line picture signal, respectively.
In such a circuit arrangement, first, the first half, 15 bits (first bit to fifteenth bit) of a first line picture signal (which is assumed to be formed of 30 bits) are supplied from the picture signal generator 15 to the RAM 18a and written therein, and the second half thereof, or 15 bits (sixteenth bit to thirtieth bit) are similarly written in the RAM 18b. Then, the first half, 15 bits of the next scanning line picture signal are written in the RAM 18c, and second half, or 15 bits thereof are written in the RAM 18d. While the second scanning line picture signal is being written, the first scanning line picture signal stored in the RAMs 18a and 18b is supplied by 3 bits at a time to the shift registers 19a and 19b, respectively. The contents in the shift registers 19a and 19b are supplied through drivers 20a and 20b to the picture signal input terminals 21 of the heat-sensitive heads 22, respectively.
In the first printing, three bits consisting of the first bit to third bit of the first scanning line picture signal are supplied to the shift register 19a, and at the same time three bits consisting of the 30th bit to 28th bit thereof are supplied to the shift register 19b. In the second printing, the three bits of the second block on the left half in FIG. 1 are read and the three bits of the second block on the right half are read. In this way, the line can be recorded with less steps which are more inconspicuous, as shown in FIG. 2.
The recording circuit of FIG. 3, however, is formed of a number of circuit elements and the detailed practical circuit of FIG. 3 is complicated. The conventional method of renewing the read address to the RAM in which data is recorded utilizes, for example, an up-counter suitable for a matrix arrangement, which is connected to the address input of the RAM. Thus, when a new modified matrix arrangement is used therein, it is necessary to change the control circuit for the counter and RAM, and hence, such a single-matrix arrangement circuit is limited to very few variations.
For example, Japanese Patent Application Laid-open No. 158,774/80 discloses a control circuit for matrix drive printing.